The present disclosure relates to semiconductor manufacturing, and particularly to system and method for performing simultaneous lithography and etch processes correction flow.
In an example “tape out” flow, i.e., where data processing methods and simulations are implemented for building a single mask and/or correcting for lithographic errors for semiconductor layer design, the method, in one embodiment, enables a move (e.g., a shifting) of individual mask polygons to account for any predicted overlay errors, for example, in or during an Optical Proximity Correction (OPC) step. OPC is used to correct for lithographic nonlinearities by performing simulations, modeling the lithography process, and for example, based on modeling correct for optimizing the mask size, e.g., (change the mask size). Performing OPC processes thus delivers a mask “shape” and the mask data (of the shape) is used to form (print) mask and the printed mask used in a lithographic process to form a semiconductor feature.
As critical dimension continue to shrink beyond 22 nm technology node, the process window for each process step reduces accordingly. As a result, after performing a lithographic printing process using the OPC designed mask, it is seen that resulting etch steps fail significantly in multiple critical design configurations when using etch processes after lithography, e.g., a Reactive Ion Etch (RIE).
Thus, OPC provides a mask shape which is used to build a mask and use of the correct lithography will print the feature. However, due to RIE etch phase processing, the printed features on a substrate are increasingly failing.
Ideally, there is a set of process conditions where there are no failures found. This set of conditions is the process window (PW) i.e., range of focus and dose variation where wafers can be printed without failure. Masks created must have tolerance to these process variations. For example, as known, a focus exposure matrix governs the wafer processes, with some variations placed in to account for the manufacturing process variables. In lithography, it is the focus and exposure dose (i.e., how well focus is held, and the amount of light (exposure dose)) that are the primary variables in lithography. Focus and Exposure and dose variations are generated into a matrix, and the wafer is exposed through patterns of focus and dose variations to generate the matrix. The patterns are measured across all process and exposure conditions.
It is the case that in patterning, within a “process window” (PW), the boundaries of lithography and etching have been conflicting each other and resulting in optimizing each of them independently will push the other in hard fails, particularly as the technology moves to 22 nm and beyond.
As a particular example, one type of excessively determined failure is resist top loss induced fails on etch at a hard mask open (“HMO”) (HMO etch process) step.
FIG. 1 shows an example photoresist material top-loss phenomenon, and failed pattern transfer through etch. A top down view shows a pair of mask edges 12A, 12B defining a gap 15 for deposition of a resist layer 18 on a wafer as shown. As shown in FIG. 1, graph 13 shows the normalized resist thickness that results as a function of applied light (exposure) to the resist layer. As shown, no material loss is exhibited with low dose exposure. As shown on the accompanying graph 13, after an exposure, ideally the photoresist layer would not lose any material until such a large enough dose is applied (e.g., a critical dose) with an ideal amount of light exposure. However, due to this resist characteristics, it loses its thickness/volume from its original level 11, i.e., resist top loss (resist height level is decreased) when scattered photons hit the un-exposed area. That results in the pattern pinching and cannot be transferred through etch. Different design configurations lead to different levels of latent (resist) intensity 19, and the degree of resulting resist heights may vary, e.g., as shown in resist features 18A, 18B or 18C for a same critical dimension (CD). That is, only the height of the resist is affected but not the CD, i.e., bottom dimension (due to variation of focus and/or dose (process variation), mask design shape, etc.).
In the lithographic modeling employed, SEM measurements are made to the bottom critical dimension (CD) to measure the width and/or space at the bottom of the resist. As only resist height changes the lithographic model has no knowledge of the resist height change.
Due to the resist characteristics (FIG. 1 graph 13), the exposes resist loses its thickness/volume when scattered photons hit the un-exposed area. That results in the pattern pinching and cannot be transferred through etch causing etch fails due to the HMO fails.
FIG. 2 shows a resulting wafer image 10 depicting electron-beam inspection (EBI) tool result showing multiple post RIE etch process fails 25 on multiple mask exposures/dies 30 of a wafer 20 (at a particular set of focus and does process conditions). Particularly, FIG. 2 shows an example 22 nm processing with errors at an “Mx” metal level. Here, the EBI inspection at post HMO shows no PW. Both lithographic modeling and ORC (Optical Rule Checking) could not predict the wafer fails 25 from EBI. This ORC is a simulation of the mask and checks (measurements) applied to look for problem spots (potential failures) during the wafer. The wafer fails 25 post etch shown were not predicted, i.e., the normal lithographic models could not predict this type of failure mechanism.
It is the case that a conventional OPC correction flow cannot capture the correct fail mechanism and cannot drive the mask size to an optimized common process center between lithography and etch.
Further, a lack of good etch models leads to patterning failures, e.g., a photoresist bottom CD may be in-spec, but as mentioned, fails post etch. The fails are correlated with photoresist toploss, but toploss or 3D resist profile is difficult to measure directly and model accurately. Moreover, any etch models employed tend to be inaccurate and have resulted in non-manufacturable lithographic conditions. For example, etch models lack “process window” simulation capability: 1) due to assumption that etch bias only depends on pattern density terms; and 2) there is no connection to lithographic pattern fidelity or 3D resist profile.
Moreover, while a 3D resist simulation is expensive and not appropriate for a full chip analysis, such a resist simulation could be used to build a more physical and more accurate etch model.
Moreover, when modeling a patterning process, typically separate models are built for the optical photolithograpy process and the etch process. The photolithograpy model involves both an optical model that describes the light formation in the exposure tool and a photoresist model that describes the exposure and development of the photoresist. These models are often calibrated to a single set of measurements taken in the post-develop photoresist using a CD-SEM. CD-SEM measurements are typically made at the bottom of the photoresist and measurement artifacts are removed through a SEM-to-physical bias correction applied to the bottom CD measurements. The etch process is typically modeled as a variable bias between the post-develop and the post-etch measurements. This variable bias is found as a function of parameters related to the pattern density of the post-develop pattern. If the photolithography is of adequate quality, the pattern density of the lithography design target can be used as a proxy for the patterned photoresist, resulting in improved simulation efficiency.
However, this approach does not fully account for the complex interactions between the 3 dimensional photoresist profile, the CD-SEM measurement capabilities and the transfer of a pattern in photoresist into a film stack through an etching process. Since the etch transfer may depend on the 3 dimensional profile of the photoresist, in addition to other factors traditionally considered in etch models such as local pattern density, it is reasonable to consider the full resist profile in creating a physical etch model.
However, 3D resist profile simulations are expensive and time consuming, and are, therefore, not suited for full chip etch modeling.